Method of altering the properties of a thin film and substrate implementing said method

ABSTRACT

The invention relates to a process for modifying the properties of a thin layer ( 1 ) formed on the surface of a support ( 2 ) forming a substrate ( 3 ) utilised in the field of microelectronics, nanoelectronics or microtechnology, nanotechnology, characterised in that it consists of: 
         forming at least one thin layer ( 1 ) on a nanostructured support with specific upper surface ( 2 ),    and treating the nanostructured support with specific upper surface ( 2 ) to generate internal strains in the support causing its deformation at least in the plane of the thin layer so as to ensure corresponding deformation of the thin layer to modify its properties.

The present invention relates to the field of producing substratescomprising at least one thin layer formed on the surface of a support,such substrates being utilised in the fields of microelectronics,nanoelectronics or microtechnology, nanotechnology in a general sense.

The present invention has particularly advantageous applications in thefield of materials having electronic, optoelectronic, supra-conductor orpiezoelectric functions for example.

For instance, certain electronic and optoelectronic applications cannecessitate the use of ternary or quaternary semiconductor materials.However, the number of these ternary and quaternary materials of highstructural quality possible to obtain by epitaxial growth is limited asit is rarely possible to find a substrate whereof the crystallinenetwork is adapted to that of the semiconductor layer to be grown.Consequently, heteroepitaxy carried out in lattice conflict causesformation of a significant quantity of structural defects beyond acritical thickness, which then causes irreversibly undesirablemodifications of the expected physical properties of the epitaxiedlayers. Furthermore, the use of strained compound or simplesemiconductor layers can be for profiting from the improvement ofcertain properties. There again, the use of a technique for deformingthe layers homogeneously would be an advantage.

To try to eliminate these problems, growth techniques have beendeveloped including producing buffer layers whereof the objective is toabsorb the strains induced by the difference in the lattice parametersbetween the substrate and the epitaxied thin layer.

A first family of techniques aims at using compliant substrates consistsof producing epitaxy in conflict with lattice on a fine membrane,serving as a nucleus layer. The strain energy is thus supposed to berelaxed elastically or plastically by the membrane.

By way of example a technique of elastic compliance of a nucleusmembrane has been described by S. I. Romanov et al., Appl. Phys. Lett.75, (1999) p. 4118.

This technique consists of:

-   -   porosifying the surface of a substrate of Si so as to form two        porous layers with specific upper surface, with the surface        layer presenting low porosity while the latter which is inserted        between the surface layer and the substrate exhibits increased        porosity,    -   lightly oxidising (maximum monolayer) the surface of the        resulting substrate so as to mechanically stabilise the        crystallites,    -   deoxidise the substrate in the growth structure just prior to        epitaxy of a fine layer of Si, and    -   producing growth in conflict with lattice of a layer of SiGe on        the fine layer of Si.

The process described by Romanov et al thus comprises generatingepitaxial growth in conflict with lattice on a membrane of Si obtainedon porous Si. An effect of compliance (deformation) of the porous layersseems to be observed.

Different studies on the compliant substrate have been carried out. Thearticle by A. M. Jones, Appl. Phys. Lett. 74, (1999) p. 1000 can becited by way of example, describing a growth technique on a freemembrane aimed at depositing on a substrate two layers, namely a firstlayer which is called sacrificial and then the fine membrane on whichepitaxy is performed. The sacrificial layer is a layer whereof thechemical attack speed for a solution is considerable before that of themembrane. A lithographic step is taken to have only one disc of themembrane subsist at the surface of the sample which is then dipped inthe chemical attack solution. The sacrificial layer is etched, includingunder the disc, by sub-etching. The chemical attack is stopped whenthere is only one pillar remaining to carry the disc of the membrane onwhich is formed the growth of an epitaxied layer. The membrane is thuscapable of deforming to limit the deformations of the epitaxied layer.The advantage of this method is that the epitaxied layer strain isrelatively well relaxed elastically. However, this method has a numberof disadvantages such as fragility of the structure, non-planarity ofthe surfaces, difficulty of the production process and the small size ofthe zones obtained.

A method of misaligned fusion or << twist bonding >> can also cited, asdescribed especially in the article by Y. H. Lo, Appl. Phys. Lett. 59,(1991) p. 2311, transferring a membrane strain or not, on a substratehost by ensuring the generation of a rotation between thecrystallographic directions of the membrane and that of the substrate.This creates a network of dislocations at the interface between themembrane and the substrate. This produces a growth of a strain layer onthe membrane. Under the effect of the strain energy the dislocations aresupposed to change orientation to take on a corner character and thusminimise this energy. The advantage of this technique bears on thetransfer of the membrane on the totality of the substrate. However,there is no guarantee of the resulting relaxation and there are doubtson the homogeneity of the resulting relaxation.

By way of example also the technique of molecular adhesion or << waferbonding >> can be cited, as described especially in the article by D. M.Hansen et al., J. Cryst. Growth. 195, (1998) p. 144, aiming attransferring a membrane by molecular adhesion on a surface-oxidisedsubstrate. The growth of the layer strain is then produced on themembrane. The atoms of the membrane presented at the interface caneffect slight displacements for relaxing the strain layer. The principaladvantage of this technique is the large size of the resulting surfaces.All the same, even if a compliance effect is observed, the relaxation isnot total. The critical thicknesses of the deposited layers areincreased, but it is still not possible to produce thick layers exemptfrom structural defects.

All these compliance plastic or elastic techniques do not exhibit theexpected characteristics. Plastic or elastic deformation of the nucleuslayer by the epitaxial layer is not or is only partially observed. Onthe other hand, the lateral dimensions of the resulting zones exemptfrom defects are too slight.

In the prior art, another family of known solutions relates to theparamorphic technique consisting of undertaking epitaxy of a strainmembrane then of having it relax elastically to then undertake epitaxycommensurate with lattice. The aim of this technique is to successivelydeposit on a substrate a sacrificial layer and a strain membrane viaepitaxy. A lithographic stage then selectively etches the membrane toproduce the discs. Humid chemical etching is carried out to totally etchthe sacrificial layer, including under the discs by sub-etching. Thestrain membrane relaxes elastically while it is no longer maintained.This strain membrane is then deposited on the substrate. The principaladvantage of this technique comes from reprise of growth commensuratewith lattice. However, the discs obtained are limited in size (a fewhundred microns) and the conflicts of the initial parameters of themembrane are low (1% environ).

Another family of solutions described by D. S. Cao., J. Appl. Phys. 65,(1989) p. 2451 is the metamorphic method with use of buffer layers offixed or gradual compositions or even super-networks. The buffer layershave a lattice parameter which is different to that of the substrate.Growth of these layers is generated for thicknesses greater than thecritical thickness. The buffer layer thus relaxes via generation ofdislocations and retrieves its non-strained lattice parameters. Thegrowth of the desired active layer is thus realised on these bufferlayers of lattice parameters different to those of the originalsubstrate. The first difficulty of this technique originates fromconfinement of the dislocations in the buffer layer which is not total,emerging dislocations always being presented in the active layerdegrading the properties of the latter. The second originates from theappearance of coarseness at the surface of the buffer layer which candegrade the expected properties of the active layer.

The prior art has also proposed via document JP 2000 0091 627 atechnique for manufacturing light emitters consisting of making adeposit of a polycrystalline material with fine grains, followed bythermal treatment. This annealing allows atomic rearrangement whichleads to the increase of grain size. However, this technique gives noguarantee for homogeneity of reorganisation and does not generateepitaxial growth of any layer commensurate with lattice with itssubstrate.

The result of analysis of the different techniques known to date is theobservation that they do not give satisfaction in practice. There is theapparent need to be able to utilise a technique effecting the epitaxialgrowth of any layer commensurate with lattice with its substrate.

The applicant has expressed the need to be able to make use of atechnique for modifying the lattice parameters of a substrate to allowepitaxy commensurate with lattice of alloys having at least two chemicalelements. To satisfy this need, the applicant proposes a technique formodifying the lattice parameter of a thin layer, strain or not, madedirectly or indirectly on a support together forming a substrate. Moregenerally, this technique allows not only the lattice parameter to bemodified, but also various other properties of a thin layer deposited onthe surface of a support forming a substrate able to be used in thefield of microelectronics, nanoelectronics or microtechnology,nanotechnology.

The object of the invention relates to a process for modifying theproperties of a thin layer. The process according to the inventionconsists of:

-   -   forming at least one thin layer on a nanostructured support with        specific upper surface,    -   and treating the nanostructured support to generate internal        strains in the support causing its deformation at least in the        plane of the thin layer so as to ensure corresponding        deformation of the thin layer to modify its properties.

According to a preferred variant embodiment the process consists oftreating the nanostructured support with specific upper surfacechemically to ensure deformation corresponding to a dilation orcontraction of, its nanostructure.

According to a characteristic of the invention the process consists ofselecting a nanostructured support with specific upper surface fromamong diverse nanostructures based on metals, semi-conductors ordielectric materials.

According to preferred variant embodiment the process consists, aftertreatment of the nanostructured support with specific upper surface, ofgenerating on the thin layer epitaxial growth of a crystalline material.

Preferably, the process consists of selecting a thin layer capable ofhaving after treatment of the nanostructured support with specific uppersurface a lattice parameter corresponding to the lattice parameter ofthe crystalline material to be formed by epitaxial growth on said thinlayer.

Preferably, the process consists of forming on the nanostructuredsupport with specific upper surface a thin layer prestrained or not.

According to a variant embodiment the process consists of forming on thenanostructured support with specific upper surface at least oneintermediate layer between the thin layer and the nanostructured supportwith specific upper surface.

Advantageously, the process consists of forming on the thin layer theepitaxial growth of a crystalline material selected from amongsemiconductor, magnetic or supra-conductor materials.

Advantageously still, the process consists of forming on thenanostructured support with specific upper surface a thin layer made ofa material having piezoelectric properties.

According to a variant embodiment, the process consists of effecting onthe thin layer a lithographic operation to have piezoelectriczones-appear.

According to another variant embodiment the process consists ofdeforming the nanostructured support with specific upper surface so thatelectrical charges appear at the level of the thin layer.

Another object of the invention is to propose a substrate formicroelectronics, nanoelectronics or microtechnology, nanotechnology,formed by a nanostructured support with specific upper surface anddeformed following treatment and on the surface of which is at least onethin layer deformed corresponding to the support.

Advantageously, the substrate comprises an epitaxial layer of acrystalline semiconductor, magnetic or supra-conductor material, formedon the thin layer.

Advantageously, the substrate comprises a thin layer made of anpiezoelectric material.

Another object of the invention focuses on the application of thesubstrate to creating an optoelectronic element.

Another object of the invention focuses on the application of thesubstrate to creating an electronic component.

Various other characteristics will emerge from the following descriptionin reference to the attached diagrams which show, by way of non-limitingexamples, embodiments of the object of the invention.

FIG. 1 illustrates a substrate to which is applied the process accordingto the present invention.

FIGS. 2 a to 2 d illustrate the different phases of a first exampleembodiment of a substrate comprising a thin layer adapted to epitaxialgrowth.

FIGS. 3, 3 a, 4 a, 5 a illustrate the different phases of a firstvariant embodiment of a substrate utilising the process according to thepresent invention.

FIGS. 3 b and 4 b illustrate the different phases of a second variantembodiment of a substrate using the process according to the presentinvention.

FIGS. 6 a, 6 b, 6 c illustrate the different characteristic phases ofthe process according to the present invention used for a piezoelectricmaterial.

As evident from FIG. 1, the object of the invention relates to a processfor modifying the properties of a thin layer 1 created on the planarsurface of a support 2 forming a substrate 3 for use in the fields ofmicroelectronics, nanoelectronics or microtechnology, nanotechnology.

The process according to the invention consists of taking ananostructured support 2 presenting a specific upper surface, that is, asupport which contains at least one layer constituted bynanocrystallites and/or nanoparticles of various geometric shapesinterconnected between one another and whereof at least one dimension isless than or equal to 1,000 nm and whereof the sum of the surfaces ofeach nanocrystallite and/or nanoparticle is greater than the planarsurface occupied by said layer. Diverse nanostructured materials canutilised to make up the nanostructured support 2 according to theinvention, for example:

-   -   nanostructures with specific upper surface based on metals or        semi-metals,    -   semi-conductor nanostructures with specific upper surface such        as for example porous silicon or other semi-conductor        nanostructures of type IV, IV-IV, III-V, II-VI, etc.,    -   or nanostructured dielectric materials with specific upper        surface based on TiO₂ (anatase, rutile), Al₂O₃, ZnO, etc.

The process according to the invention aims to form or effect on theplanar surface of the nanostructured support 2 at least one strain thinlayer 1. This strain thin layer 1 is either attached directly orindirectly to the nanostructured support 2 by means for example ofadhesion utilising molecular adhesion means, or deposited by any method,or made from the nanostructured support 2.

The thin layer is made of a material dependent on the applicationenvisaged for the substrate 3, such as, for example, a metal, adielectric, a semi-conductor or a polymer of any types.

The process according to the invention then aims at treating thenanostructured support 2 to generate internal strains in the support,causing its deformation at least in the plane of the thin layer 1 so asto modify its properties. The nanostructured support 2 is treated so asto change its volume, that is, to dilate it or to contract it such thatthe thin layer 1 subjects the interface between the nanostructuredsupport 2 and the thin layer 1 to the same deformation as thenanostructured support 2. The thin layer 1 is then in tension orcompression.

It must be understood that the internal strains generated in thenanostructured support 2 by the treatment then relax, partially orcompletely, by deformation of the nanocrystallites and/or nanoparticleson a nanometric scale causing macroscopic deformation of thenanostructured support 2.

The means utilisable to generate these internal strains are multiple andcan be used either separately or conjointly. One of these means consistsof modifying the physico-chemistry of the nanocrystallites and/ornanoparticles. By way of example, modification of the chemistry of thenanocrystallites causes variations in average interatomic distances ofthe atoms forming the nanocrystallites. These modifications of achemical nature translate by internal strains appearing on a nanometricscale which relax by deformation of the nanocrystallites while causingmacroscopic deformation of the nanostructured support. Other meansconsist of filling the void present between the nanocrystallites byinserting material (for example during deposit in vapour phase). Thisaddition of material comprises the nanocrystallites which deform. One ofthe advantages of this technique is to help modify the global thermaldilation coefficient of the support by selecting the nature of thedeposits made between the nanocrystallites so as to have thiscoefficient correspond to that of the epitaxied layer. The treatmentoperation of the nanostructured support 2 aimed at assuring itsdeformation is carried out by any appropriate means, such as chemical,for example.

The process according to the invention thus assists in varying thevolume of the nanostructured support 2, using a dilation or contractioneffect, so as to ensure the corresponding deformation, namely dilationor contraction of the thin layer 1 at the interface with the support.Such a process modifies the properties of the thin layer 1, such asphysical or morphological (variation of the lattice parameter,thickness, . . . ), electrical (raising of the degeneracy of the valenceband in the semi-conductor, appearance of charges for the piezoelectriclayers, change on dielectric constant, modification of electricaltransport properties such as for example the variation in electron andhole mobility in silicon, . . . ), magnetic (change in the Hysteresiscycle with modification of crystalline symmetry for ferromagneticmaterials) or optical (modification of the absorption energy of thephotons, refraction index, . . . ).

The process according to the invention produces a substrate 3 not havinga size limit, while being compatible with the nano- or microtechnologiesof collective fabrication of components. This solution also has theadvantage of reduced manufacturing costs.

FIGS. 2 a to 2 d illustrate a first variant embodiment of a substrate 3produced by the process according to the invention and destined topermit growth of an epitaxial layer commensurate with perfect orquasi-perfect lattice.

FIG. 2 a illustrates a support 2 nanostructured partially by a processenabling the nanometric porosification of its crystalline structure orby a process enabling growth of a nanostructured layer on its surface.The nanostructured support 2 partially comprises a non-nanostructuredlayer 2 ₁ and a nanostructured layer 2 ₂. Of course, the layer 2 ₁ canbe made up of a series of layers of different chemical nature. Thislayer 2 ₁ can be of a different chemical nature or not to the layer 2 ₂.This layer 2 ₁ can be strained relative to the layer 2 ₂ prior to thedeformation operation. Similarly, it should be noted that the object ofthe invention can be implemented with a completely nanostructuredsupport 2.

In the illustrated example, the nanostructured support 2 comprises alayer 2 ₁ of monocrystalline silicon and a layer 2 ₂ of nanostructuredporous silicon. As is evident more precisely from FIG. 2 b, a thin layer1 is produced on the support, that is, on the layer nanostructuredporous silicon 2 ₂. This thin layer 1 is for example constituted byindium phosphorous (InP) and is made via epitaxy by molecular jets orother.

As is evident more precisely from FIG. 2 c, the support 2 is subjectedto treatment, for example chemical, such as oxidation, hydrogenation orthe like, allowing the state of strain in the nanostructured support 2to be strongly modified, causing dilation or contraction of itsnanostructure. This dilation or contraction of the nanostructuredsupport 2 causes corresponding dilation or contraction of the thin layer1 at the interface with the nanostructured support 2. The contraction ordilation of the nanostructured support 2 respectively diminishes oraugments the lattice parameter of the thin layer 1 in the plane of theinterface.

The process according to the invention then consists of processing at anepitaxy 4 for example in perfect lattice accord on the free surface ofthe deformed thin layer 1. For example, epitaxy of a layer of InGaAs canbe undertaken on a thin layer of deformed InP.

FIGS. 3, 3 b and 4 b illustrate another example embodiment of asubstrate implementing the process according to the invention andfocussed on eliminating the assembly stage of the nanostructured supportwith the thin layer. As is evident more precisely in FIG. 3, the support2 is nanostructured partially by a process allowing nanometricporosification of a part of its crystalline structure or by a processallowing the growth of a nanostructured layer. The support 2 comprises anon-nanostructured layer 2 ₁ and a nanostructured layer 2 ₂. This layer2 ₁ can be strained relative to the layer 2 ₂ prior to the deformationoperation. What is more, the layers 2 ₁ and 2 ₂ can be of a differentchemical nature or not. For example, the support 2 comprises a layer 2 ₁of monocrystalline silicon-germanium (Si_(x)Ge_(1-x)) and a layer 2 ₂ ofnanostructured silicon. The layer 2 ₁ of monocrystalline Si_(x)Ge_(1-x)is controlled in thickness so as to constitute the thin layer 1. As isevident more precisely from FIG. 3 b, such a nanostructured support istreated to ensure its deformation, so as to assure correspondingdeformation of the thin layer 1 of monocrystalline Si_(x)Ge_(1-x). Asexplained hereinabove, this deformation operation has the latticeparameter of the thin layer 1 of monocrystalline Si_(x)Ge_(1-x) vary inthe plane of the interface enabling as illustrated in FIG. 4 b anepitaxy operation 4 of a crystalline material such as GaAs commensuratewith lattice.

FIGS. 3 a to 5 a illustrate another variant embodiment for carrying intoeffect the process according to the invention from a nanostructuredsupport 2 described in FIG. 3 also aimed at creating the thin layer 1above at least one intermediate layer of monocrystalline silicon 2 ₁ ofthe nanostructured support 2. The criteria for selecting the thicknessof this intermediate layer 2 ₁ are the same as for the thin layer 1. Athin layer 1, for example indium phosphorous, is formed on thisintermediate layer 2 ₁ of monocrystalline silicon. According to FIG. 4a, such a support 2 is treated to ensure its deformation permittingmodifying of the lattice parameter of the thin layer 1 of indiumphosphorous. Of course, the lattice parameter of the layer 2 ₁ ofsilicon monocrystalline has also changed. As is evidenced more preciselyin FIG. 5 a, epitaxy 4 of a crystalline material such as an InGaAs layercan be undertaken on the thin layer 1 of indium phosphorous. Thisvariant can be utilised if producing the thin layer 1 is easier on thelayer of monocrystalline silicon 2 ₁ than on the layer of porousnanostructured silicon 2 ₂. In general, it is evident that in the casewhere the nanostructured support 2 is partially nanostructured, thelayer 2 ₂ represents the nanostructured part of the support and thelayer 2 ₁ represents the non-nanostructured part.

As is evident from the preceding description, the thin layer 1 isselected so a to have, after treatment of the nanostructured support 2,a lattice parameter corresponding to the lattice parameter of thecrystalline material to be formed by epitaxial growth on said thin layer1. It should be noted that the thin layer 1 can be formed or made on thenanostructured substrate 2 in the prestrained form or not. In addition,the thin layer 1 is formed or made on a support 2 not yet or alreadynanostructured.

The thin layer 1 has a thickness determined as a function of twocriteria:

-   -   the thin layer 1 must be of a sufficiently slight thickness        before the nanostructured support 2 to prevent, after        deformation, excessive curving of the substrate (nanostructured        support and thin layer),    -   the thin layer must be of a sufficiently slight thickness so        that deformation is generated by structural defects and thus        remains elastic in nature.

Generally, the nature of the thin layer will be selected relative to themodified physical properties expected after deformation. In theparticular case of heteroepitaxy, the material constituting the thinlayer 1 will be selected as a function of the material which must beepitaxied hereinabove so that its lattice parameters are the closestpossible to one another. For example, the thin layer 1 can havedeposited on it polymers or epitaxial growth of a crystalline materialselected from amongst the materials:

-   -   Semiconductor such as:        -   Family IV-IV: Si, Ge, Si_(x)Ge_(1-x), SiC,            Si_(x)Ge_(y)C_(1-x-y)        -   Family III-V: Ga_(x)Al_(1-x)As, Ga₁In_(1-x)As,            Al_(x)In_(1-x)As, Ga_(x)In_(1-x)As_(y)P_(1-y),            Ga_(x)Al_(1-x)P, Ga_(x)Al_(1-x)N, Ga_(x)In_(1-x)N,            Ga_(x)In_(1-x)Sb, Ga_(x)Al_(1-x)Sb,            (Ga_(x)In_(1-x))_(1-y)Tl_(y)As,            (Ga_(x)In_(1-x))_(1-y)Tl_(y)P,        -   Family II-VI: Zn_(x)Cd_(1-x)Te_(y)Se_(1-y), Cd_(x)Hg_(1-x)Te    -   Supra conductor such as YbaCuO.    -   Magnetic materials such as:        -   ferromagnetic materials such as: iron, cobalt, nickel, as            well as their alloys and some rare earths,        -   paramagnetic materials.

As is evident from the preceding description the object of the inventionrelates to a process allowing the properties of a thin layer 1previously created on a nanostructured support 2 to be modified bydeforming it to cause corresponding deformation of the thin layer.

This process produces a substrate comprising a nanostructured support 2deformed following treatment and on the surface of which is formed atleast one thin layer 1 deformed in correspondence to the support. Such asubstrate is to comprise a thin layer of any material forming the thinlayer 1. An application of this substrate is the realisation ofelectronic components for profiling modified properties contributed bythe deformation of the thin layer 1. Another possible application ofsuch a substrate is to make up an optoelectronic element by utilisingthe possibility of modifying the optical properties of the thin layerobtained by deformation of its structure.

FIGS. 6 a to 6 c illustrate another example of application of theprocess according to the invention allowing the piezoelectric propertiesof a thin layer to be used.

According to this application example, the process consists of formingon a nanostructured support 2 at least one thin layer 1 made of amaterial having piezoelectric properties. A lithographic operation isthen realised on this thin layer 1 to have piezoelectric zones z subsistsuch as is evident more precisely in FIG. 6 b. It should be noted thatdifferent types of lithographic operations such as optical, electronicor X rays could be employed.

Treatment of such a nanostructured support 2 to ensure its deformationsuch as described hereinabove leads to corresponding deformation of thethin layer 1 allowing electrical charges to appear at the level of thethin layer and especially at the level of the piezoelectric zones 3 suchas is clearly evident in FIG. 6 c. It is noteworthy that thelithographic operation can be carried out after the treatment operationof the nanostructured porous support 2 causing its deformation.

The process according to the present invention also produces a substratefor microtechnology or nanotechnology. In this way, in the case wherethe thin layer 1 formed on the nanostructured support is made: of apiezoelectric material, elements of controlled form can be obtained byusing piezoelectric properties.

The invention is not limited to the examples described and illustratedsince various modifications can be made without departing from the scopeof the invention.

1. A process for modifying the properties of a thin layer (1) formed onthe surface of a support (2) forming a substrate (3) utilised in thefield of microelectronics, nanoelectronics or microtechnology,nanotechnology, comprising the steps of: forming at least one thin layer(1) on a nanostructured support with specific upper surface (2), andtreating the nanostructured support with specific upper surface (2) togenerate internal strains in the support causing its deformation atleast in the plane of the thin layer so as to ensure correspondingdeformation of the thin layer to modify its properties.
 2. The processas claimed in claim 1, comprising treating the nanostructured supportwith specific upper surface (2) chemically to assure deformationcorresponding to dilation or contraction of its nanostructure.
 3. Theprocess as claimed in claim 1, comprising selecting a nanostructuredsupport with a specific upper surface (2) among diverse nanostructuresbased on metals, semi-conductor or dielectric materials.
 4. The processas claimed in claim 1, comprising effecting the epitaxial growth of acrystalline material on the thin layer (1), after the treatment of thenanostructured support with specific upper surface (2).
 5. The processas claimed in claim 4, comprising selecting a thin layer (1) capable ofpossessing a lattice parameter corresponding to the lattice parameter ofthe crystalline material to be formed by epitaxial growth on said thinlayer (1) after treatment of the nanostructured support with specificupper surface (2).
 6. The process as claimed in claim 5, comprisingforming a thin layer (1) prestrained or not on the nanostructuredsupport with specific upper surface (2).
 7. The process as claimed inclaim 1, comprising forming on the nanostructured support with specificupper surface (2), at least one intermediate layer (2 ₁) between thethin layer (1) and the nanostructured support with specific uppersurface (2).
 8. The process as claimed in claim 4, comprising forming onthe thin layer (1) the epitaxial growth of a crystalline materialselected from semi-conductor or superconductor materials.
 9. The processas claimed in claim 1, comprising forming on the nanostructured supportwith specific upper surface (2) a thin layer (1) made of a materialhaving piezoelectric properties.
 10. The process as claimed in claim 9,claim 1, comprising performing on the thin layer (1) a lithographicoperation to reveal piezoelectric zones (z).
 11. The process as claimedin claim 9, comprising deforming the nanostructured support withspecific upper surface (2) so that electrical charges appear at thelevel of the thin layer.
 12. A substrate for microelectronics,nanoelectronics or for microtechnology, nanotechnology, characterised inthat it is formed by a nanostructured support with specific uppersurface (2) and deformed following treatment and on the surface of whichis formed at least one thin layer (1) deformed in correspondence withthe support.
 13. The substrate as claimed in claim 12, characterised inthat it comprises an epitaxial layer (4) of a semi-conductor orsupra-conductor crystalline material, formed on the thin layer (1). 14.The substrate as claimed in claim 12, characterised in that the thinlayer (1) is made of a piezoelectric material.
 15. An optoelectronicelement comprising the substrate as claimed in claim
 12. 16. Anelectronic component comprising the substrate as claimed in claim 12.